[Libre-soc-isa] [Bug 535] setvl/setvli encoding & future reg file expansion

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=535

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #16)
> (In reply to Luke Kenneth Casson Leighton from comment #15)
> > (In reply to Jacob Lifshay from comment #14)
> > > (In reply to Luke Kenneth Casson Leighton from comment #12)
> > > > ok,ok, this is hilarious: if we allow setvl to be an SV-P48 prefixable
> > > > instruction, it *might* be possible (stress: might) to get CR0 retargetted
> > > > at an alternative CR.
> > > > 
> > > > one downside of Rc=1 is you can't doecify an alternative CR, end result you
> > > > have to move it to another CR then the bc can use that alternative target.
> > > 
> > > can't bc just use cr0 as-is?
> > 
> > yes, but think about it: intervening ops between the setvl and the
> > branchpoint will likely have trashed cr0 (other Rc=1 ops).  if either the
> > intervening ops can be retargetted or both the setvl and bc are retargetted..
> 
> Umm, wouldn't it be just:
> 
> my_fn:
> li r3, 1000
> setvl. r4, r3, 64
> beq cr0, end
> loop:
> sub r3, r3, r4
> ...
> setvl. r4, r3, 64
> bne cr0, loop
> end:
> blr

err... yes! :)

or:

my_fn:
  li r3, 1000
  b test
loop:
  sub r3, r3, r4
  ...
test:
  setvl. r4, r3, 64
  bne cr0, loop
end:
  blr

which saves one instruction and, at the same time (just as you also wrote)
avoids running empty vector instructions if VL=0 on the first iteration.

that was always an odd quirk of all RVV examples.

i don't know why, the use of CR0 just feels more natural than using a sub. on
r3 although doing so is effectively exactly the same thing.

let's hope that setting VL does not involve huge OoO resets/delays when it
comes to implementation.

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