[Libre-soc-isa] [Bug 535] setvl/setvli encoding & future reg file expansion

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=535

--- Comment #16 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #15)
> (In reply to Jacob Lifshay from comment #14)
> > (In reply to Luke Kenneth Casson Leighton from comment #12)
> > > ok,ok, this is hilarious: if we allow setvl to be an SV-P48 prefixable
> > > instruction, it *might* be possible (stress: might) to get CR0 retargetted
> > > at an alternative CR.
> > > 
> > > one downside of Rc=1 is you can't doecify an alternative CR, end result you
> > > have to move it to another CR then the bc can use that alternative target.
> > 
> > can't bc just use cr0 as-is?
> 
> yes, but think about it: intervening ops between the setvl and the
> branchpoint will likely have trashed cr0 (other Rc=1 ops).  if either the
> intervening ops can be retargetted or both the setvl and bc are retargetted..

Umm, wouldn't it be just:

my_fn:
li r3, 1000
setvl. r4, r3, 64
beq cr0, end
loop:
sub r3, r3, r4
...
setvl. r4, r3, 64
bne cr0, loop
blr

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