[Libre-soc-dev] Your FOSDEM 2024 talk titled 'Cologne Chip GateMate FPGA -- filling a gap between hardware and software (with a presentation of the GMM-7550 module)'

[Anton Kuzmin]

Hello Luke,

I appreciate your patience, it took me somewhat longer to get
back on track with the gmm7550.  My comments are mixed in below
with irrelevant parts removed.


On 2024-02-11 04:29, Luke Kenneth Casson Leighton wrote:

> On Sat, Feb 10, 2024 at 11:27 PM Anton Kuzmin <ak at gmm7550.dev> wrote:
> 
>> Hi Luke,
>> 
>> For some reason, my reply didn't go through on Feb, 7th,
>> it's repeated below.
> 
> got it. as list admin i approved the cc post to libre-soc-dev list.
> if you sent to me privately, email is unlikely to get through.
> (long story)

Noted.  What would be the most reliable way to reach you,
perhaps, without involving the list?


>> about the possibility (sponsored, NLnet) of doing a run of
>> gatemate boards using the largest FPGA that they have,
>> and an external multi-IC HyperRAM Module to get up to 512 mb RAM?
>> 
>> Sounds interesting and I do not immediately see any problem.
>> Just two questions right away: 512 MiB (half GiB)
> 
> yes.

Does it make sense to have two channels in parallel,
with 4 Hyper-RAM chips on each?  The benefits are doubled
bandwidth and better routing and signal integrity,
while extra IOs on the same module connector
are not likely to be usable for anything else.

I would also suggest adding a QSPI NOR to the same module
for an extra non-volatile storage.


>> or just 64 MiB
> 
> try running linux in that. latest kernels - latest *kernels* let alone
> any userspace applications running *under* that linux kernel  -
> barely fit into 64 Megabytes of RAM.

Understood.  Is it a requirement to run Linux on it?
Are there any other OS in plans? Maybe Zephyr?


>> (512 Mbit)?  And why HyperRAM
> 
> because the HDL is about 150 lines of code and was
> operational in under 2 weeks flat on not just one FPGA
> but two completely separate ones.
> https://libre-soc.org/HDL_workflow/HyperRAM/
> 
> by contrast:  2 *years* of trying to get DDR3 operational
> (thousands of lines of complex HDL) has been unsuccessful so far,
> and SDRAM1 is a parallel bus which takes up too many
> wires.

Understood.  Indeed, DDRx without a dedicated hard-core
controller and PHY is a pain... sometimes even with the
hard controller.


>> -- that seems to be somewhat niche
>> and targeted primarily to automotive?  Would Infineon
>> S80KS5123 be suitable?
> 
> likely the S80KS5122 but you'd need to check. there's
> already a Quad HyperRAM PMOD from 1bitsquared.de
> with full source code of the PCB

You are right, the former chip (with '3' at the end of part number)
has Octal-SPI interface, not HyperBus.


>> FYI, since I saw some interest in buying the module
>> on ORconf'23, I'm trying to setup a campaign at GroupGets, but
>> there are still a few things to address, both technical and
>> businesswise.
> 
> indeed :) well applying for an NLnet grant would help at
> least cover the technical aspects and get the PCB(s) funded.
> i can introduce you to someone who can help with the
> (simpler) HyperRAM PMOD PCBs?


Yes, that would be great, thank you.


Best regards,

Anton