[Libre-soc-dev] Visual legacy

[whygee at f-cpu.org]

Hello,

On 2024-07-17 00:43, Luke Kenneth Casson Leighton via Libre-soc-dev 
wrote:
> btw yann thank you so much for posting those photos.
no need to thank, it was an opportunity to not miss and it turned out 
great !

> really must test them, needs a signal generator.
I suppose you need way more than a "signal generator".
at least create an appropriate QFP128 adapter with a ZIF socket,
then wire wrap all the relevant signals, connect appropriate
I/O chips and interfaces...

I have absolutely no idea about the pinout, the signal functions
and protocols. From what I gathered, there are JTAG TAP pins.
That's all.

You're the one who knows the design's architecture,
I guess you did all the simulations to test the validity
of the logic design but I'm sad of the lack of a physical
post-fab test plan.

What is the strategic importance of these proto/samples ?

> l.
yg