[Libre-soc-dev] NLnet Ongoing Grant
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Sep 3 09:39:19 BST 2023
btw Jacob i know it's a pig: however without the meticulous
work you did we would have made a pretty massive budget/planning
error and much worse than that lost a commercial opportunity
(the one that is confidental).
close to 100% of what is needed now is "delivering on what's
been promised". otherwise, plain and simple, we're not going
to be able to get new Grants. this is a "grit teeth and get on
with it" situation.
btw an interesting (but also very important) area would be to
add a "long multiply" REMAP Schedule. both a "same size as
input operands" as well as a "total size of input operands"
Schedule is needed.
and it also ties in directly into the commercially-confidential
opportunity as well as having the advantage of the Grant MoU
bugs under which that can be squeezed:
bear in mind Konstantinos is planning to do ed25519
(following the exact same pattern established when he did
chacha20) so the above available budget(s) need to be
the pow(x,y,mod) one can in theory be done with the
assistance of the (new) parallel-prefix REMAP to assist
in creating 1 x x^2 x^3 ... but it should *in no way*
be made complex (i.e. that is an OPTIMISATION and must
be the second iteration)
it is VITAL for the commercially-confidental
application that minimal L1 cache usage be absolute absolute
top priority over absolutely all other considerations, so
a first implementation *must* be the absolute least number
of instructions possible.
On Sunday, September 3, 2023, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Sun, Sep 3, 2023 at 6:58 AM Jacob Lifshay <programmerjake at gmail.com>
>> before we do that, if PO9 will ever have any 32-bit insns
> never. that decision has already been made.
MitchAlsup Aug 16, 2023, 7:23:04 PM (10 days ago)
On Wednesday, August 16, 2023 at 12:04:50 PM UTC-5, pec... at gmail.com wrote:
> Unfortunately they (risc nazi) managed to add compressed floating point
Which violates the main tenet of RISC ISA design::
"Architectural Tradeoffs in the Design of MIPS-X" Paul Chow and Mark
....."The goal of any instruction format should be:
..........1. Simplify Decode
..........2. Simplify Decode
..........3. Simplify Decode
Any attempts at improved code density at the expense of CPU performance
be ridiculed at every opportunity"
And RISC-V chewed up 3/4 of the Major OpCode space, lost 16-bit
for a gain of code density............and screwed up the Decoder at
the same time.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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