[Libre-soc-dev] Fwd: [Core_Fund] nlnet_2023_simplev_binutils at libre-soc.org

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Nov 30 15:04:50 GMT 2023

ok folks the second NLnet grant in the series is submitted,
now begins over the next... 4-5 weeks... the process of
creating the top-level milestone bugreports, so that when
the "good news you moved to phase 2 here are the questions
you need to answer in UNDER 48 HOURs are attached"
we can be ready immediately.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

---------- Forwarded message ---------
From: <dashboard at nlnet.nl>
Date: Thu, Nov 30, 2023 at 2:54 PM
Subject: [Core_Fund] nlnet_2023_simplev_binutils at libre-soc.org
To: Libre-SOC Project <nlnet_2023_simplev_binutils at libre-soc.org>
Cc: <2023-12-121 at nlnet.nl>

Dear Libre-SOC Project,

A proposal for a grant application was sent to NLnet Foundation
(https://nlnet.nl) using this email address. Your project has received
code 2023-12-121. The text of the proposal is shown below for your
records. If you want to make changes to this proposal before the
deadline, feel free to resubmit. We will send you a follow-up email
after the deadline has passed to provide more information regarding
the review process.

Important: if this request did NOT originate from you (and you are
unaware of others that could have made this application on your
behalf), do NOT CLICK on any links in this message nor open
attachments. Please notify us if this is the case, otherwise you can
expect at least two other emails from us. If that is not a problem,
feel free to discard immediately.

Best regards,
the NLnet team

Code        : 2023-12-121
Requestor   : Libre-SOC Project
Email       : nlnet_2023_simplev_binutils at libre-soc.org
Phone       : +447598523119
Organization: Libre-SOC Project
Country     : UK, Europe, others
Consent     : You may keep my data on record
Call        : Core_Fund
Project     : Binutils with Simple-V ISA Expansion Project
Website     : https://libre-soc.org/nlnet_2023_simplev_riscv_binutils
Abstract    : This project is to enhance binutils tools to continue
the autogenerated support
for the
RISC-V, Power and other ISAs, and to also support Simple-V
Vectorisation capabilities.
It will directly support the ISA Expansion project
for which a separate grant application has been made, and will build
on learnings from
binutils developed for POWER ISA and SVP64/Power. The outcome of the
project will be the completion of binutil tools capable of creating
and managing binary program files, including handling object files,
libraries, profile data, and assembly source code, as well as
providing a machine-readable database and associated library for other
projects to
manipulate supported Instruction sets.

Experience  : A sequence of projects enabled early development (four
years ago, 2019-03-012)
of vectorisation techniques in the RISC-V domain, and later higher performance
demonstration with OpenPOWER ISA (2022-08-051). A full project list is
maintained at: https://libre-soc.org/nlnet_proposals/ they include

* https://libre-soc.org/nlnet_2022_opf_isa_wg/ - improving SVP64 and
submitting it to the OpenPOWER ISA Technical Working Group.
* https://libre-soc.org/nlnet_2021_crypto_router/ - proving,
improving, and demonstrating that SVP64 is capable of handling
cryptographic primitives in an extreme power-efficient compact way as
the basis for higher security products

Amount      : € 85000
Use         : Key phases of this project are:

* Completion of libopid (an instruction database parser)
* Completion of libopid porting of Libre-SOC infrastructure both
Scalar Power ISA
  and SVP64/Power (currently based on an early iteration of libopid)
* Definition of assembler and disassembler for RISC-V
  instructions and also SVP32, 48 and 64 Vector Prefixing formats, using libopid
* Completion of definitions of Simple-V/Single formats SVP64Single,
SVP48Singe and SVP32Single
  and implementation support of the same for both Power and RISC-V
* Test vectors for libopid and binutils
* Documentation, demonstrations and Conference Papers.

Comparison  : There are a few machine-readable instruction databases
around: they tend not to
be used massively extensively to for example auto-generate c code for use in
binutils. Most assembler/disasembler instruction parsing oddly is done
by hand-editing
each and every instruction (10,000 in the case of Power ISA). This
project is pretty unique
and includes auto-code-generation so as to avoid transliteration
errors between ISA Spec
and source code.

Challenges  : The key technical challenge in this project is the
creation of the binutils assembler/disassembler that enables
developers to take advantage of the Simple-V/SVP64 extensions and
capabilities for RISC-V, and to successfully develop and debug complex
code. The assembly and disassembly parsing tools, which will be
general-purpose well beyond just binutils and have significant value
for machine-parsing of Instruction Sets in general, will be
comprehensively tested and verified with the newly developed
instructions (developed within the separate project) in order to lead
the way for its use in the widespread developer community.

This project relies on the experience and expertise of a subset of the
RED Semiconductor/LibreSOC team who have developed similar tools for
use with other ISAs (Power ISA in particular).
Ecosystem   :
Libre-SoC has a full set of resources for Libre Project Management and
development: mailing list, bugtrack/er, git repository, wiki and also
will be doing linkedin posts and other outreach - all listed here:

Attachments :

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