[Libre-soc-dev] daily kan-ban update 22mar2023

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Thu, Mar 23, 2023 at 5:40 AM Tobias Platen via Libre-soc-dev
<libre-soc-dev at lists.libre-soc.org> wrote:
>
> For the last memtest just one write/read cycle failed,
> the first two bytes are correct. All others are correct.
> Sometimes the Auto calibrating... fails,

even if you have it partly working this is a big deal!

auto-calibration should have a loop with some "slip" - a manual shift
of the phase
by reading those tap-points (at 90 degree points) and manually pushing them
into a hardware-queue (BitSlip) that then reads them out *shifted
over* by 1 bit,
2 bits, 3 bits, 4 bits, to compensate for the PLL *not properly
locking* in phase...

... but also compensating for the fact that some layouts and some DRAM ICs
might have variances anyway.

and if the PLL is not properly phase-locking, *different startups* give
*different results* because the data is corrupted because this time it's
phase-shifted by 90, this time it's phase-shifted by 270, this time it's
phase-shifted by 0, ......

that's the entire point of the exercise, but you *have to have the firmware
set and try different BitSlip amounts*, re-running the entire calibration
"BitSlip is zero, try the memtest. BitSlip is 90, try the memtest. BItSlip
is 180, try the full memtest ...."

l.