[Libre-soc-dev] planning next OPF ISA WG RFC: ls003, biginteger?

Jacob Lifshay programmerjake at gmail.com
Thu Mar 2 17:38:36 GMT 2023

On Thu, Mar 2, 2023, 05:11 lkcl <luke.leighton at gmail.com> wrote:

> On Tue, Oct 11, 2022 at 12:59 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > On Mon, Oct 10, 2022 at 2:31 PM lkcl via Libre-soc-dev
> > <libre-soc-dev at lists.libre-soc.org> wrote:
> > >
> > > https://libre-soc.org/openpower/sv/biginteger/
> > >
> > > whilst ls002 questions and revisions are underway, my thoughts as
> > > to the next candidate RFC would be divmod, mulx, shfl/r. sound
> > > reasonable?
> >
> > I'd like to *not* submit double-wide shift instructions just yet, as
> > part of writing the toom-cook algorithm generator I'm realizing that
> > as currently defined the shift instructions are quite difficult to use
> > as currently defined and they need some more thought/proposals.
> does this still hold, i want to get moving on the RFCs and have
> been editing ls003 to include dsld and dsrd.
> https://bugs.libre-soc.org/show_bug.cgi?id=1010

dsld/dsrd are no longer hard to use, however they still have the issue that
they unnecessarily write to `overflow`, making them much slower than
necessary because of having to read/write SO, which means you can't run
multiple instructions in parallel unless you have special dependency
hardware for SO. also, their overflow output is inconsistent with other
powerisa shift instructions.

i think we should just remove their overflow output, since that matches
other powerisa unsigned shift instructions.

(no, we can't easily match signed right shift's overflow calculation since
that needs to know the sign bit and the shifted-out bits but for bigints
those are totally separate dsrd instructions with no proper way to


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