[Libre-soc-dev] Why My 66000 is and is not RISC

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Jan 30 13:52:43 GMT 2023

On Monday, January 30, 2023, Andrey Miroshnikov via Libre-soc-dev <
libre-soc-dev at lists.libre-soc.org> wrote:
> On 30/01/2023 10:56, Luke Kenneth Casson Leighton via Libre-soc-dev wrote:
>> the same analysis applies to alignment of any-width at at-double-width.
>> this discussion is on comp.arch.
>> https://groups.google.com/g/comp.arch/c/UvprSM9xJfM
>> l.
>> ---
>> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
>> ---------- Forwarded message ---------
>> From: BGB <cr88192 at gmail.com>
>> Date: Tue, Jul 5, 2022 at 12:14 AM
>> Subject: Re: Why My 66000 is and is not RISC
>> To:
>> *1: Not sure if SH-5 was effectively also another casualty of the
>> Itanic, either way, I think at the time Hitachi folded its CPU design
>> part out to Renesas, who were apparently much more invested in keeping
>> the SH2 and SH4 going.
> I don't remember if you've mentioned this before, but have you considered
J2 (the open-hardware cleanroom implementation of Hitachi's SH-2 ISA) as
the basis of Libre-SOC? Or is it too niche to be applicable to super-scalar

there's a couple ofcandidates, SH2 which i only recently learned
about so will need to do a thorough analysis, and MyISA 6600

> I'm guessing the fixed 16-bit instructions are just too limiting to be
practical if intended to be used for large computation (not enough CPU

they can always be extended with SVP64. and just as in x86
extensive register renaming which comes effectively for
free in OoO mitgates that problem, with a few complexities
the deeper the number of in-flight instructions permitted.


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