[Libre-soc-dev] Fwd: Why My 66000 is and is not RISC

[Andrey Miroshnikov]

On 30/01/2023 10:56, Luke Kenneth Casson Leighton via Libre-soc-dev wrote:
> the same analysis applies to alignment of any-width at at-double-width.
> this discussion is on comp.arch.
> https://groups.google.com/g/comp.arch/c/UvprSM9xJfM
> 
> l.
> 
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> 
> 
> ---------- Forwarded message ---------
> From: BGB <cr88192 at gmail.com>
> Date: Tue, Jul 5, 2022 at 12:14 AM
> Subject: Re: Why My 66000 is and is not RISC
> To:
> 
> *1: Not sure if SH-5 was effectively also another casualty of the
> Itanic, either way, I think at the time Hitachi folded its CPU design
> part out to Renesas, who were apparently much more invested in keeping
> the SH2 and SH4 going.

I don't remember if you've mentioned this before, but have you 
considered J2 (the open-hardware cleanroom implementation of Hitachi's 
SH-2 ISA) as the basis of Libre-SOC? Or is it too niche to be applicable 
to super-scalar applications?

https://en.wikipedia.org/wiki/SuperH
https://j-core.org/

I'm guessing the fixed 16-bit instructions are just too limiting to be 
practical if intended to be used for large computation (not enough CPU 
registers).


Andrey