[Libre-soc-dev] cxl 3.0
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Jan 9 11:00:12 GMT 2023
On Mon, Jan 9, 2023 at 8:51 AM Jacob Lifshay via Libre-soc-dev
<libre-soc-dev at lists.libre-soc.org> wrote:
> i was reading a cxl whitepaper and apparently you can use cxl 3.0 over pcie
> 3.0's physical layer (8 Gbaud) which could be doable for our cpu... maybe
> it even supports pcie 2.0 (5 Gbaud) which the ecp5-5g can do.
nothing explicitly useful there other than links to investigate at
if opencapi is anything to go by, the protocol (ISO Layer 3+) is independent of
the transport (ISO Layer 2 and below).
> apparently you can become a cxl adopter for free, maybe the spec (the one
> you get as a member) is licensed such that implementations of cxl can be
> libre hardware, i'd have to see.
don't spend too much time on it, there are far more important tasks
to get done, which you can investigate and offer to help with.
i would expect it to be "fake-open", just like OpenCAPI was fake-open.
as in: "it's open to you only after you have signed this NDA and
Commercial Confidentiality agreement and whilst quotes free quotes
to implement you can't release any details without explicit consent
which you won't get".
if that's not the case i'll fall off my chair. fortunately it's 8in high.
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