[Libre-soc-dev] parallel reduction

[lkcl]

i've now got a parallel reduction SVSHAPE yielder which can be
plugged into ISACaller, tomorrow. it works as a standalone
demo
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/remap_preduce_yield.py;hb=HEAD

relevant sections of the spec are updated with the basics
https://libre-soc.org/openpower/sv/remap/

a new instruction should not immediately be necessary although
setting the appropriate remap options in SVSTATE may require
some finessing as a given instruction may need different settings
as to what constitutes left and right operands.

my general feeling is that the level of control over which operands
are marked as left and right for reduction purposes means that
this is the right approach.

when reduction was a "Mode" there was simply no way to specify
that (not enough bits) 

l.




On September 5, 2022 6:33:38 PM GMT+01:00, lkcl <luke.leighton at gmail.com> wrote:
>there's quite a few, lots to get done not a lot of time.
>if you continue on ls2 dram for orangecrab i can arrange
>for EUR for you if you invoice RED, around mid-october.
>
>if you want to know about parallel reduction the test
>program is here
>https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/test_preduce.py;hb=HEAD
>
>note that the number of ADD operations carried out exceeds
>the length of the vector.
>
>l.