[Libre-soc-dev] daily kan-ban update 15may2022

[Tobias Platen]

today: trying to find out why nextpnr fails when I add dram to ls2 on
the orangecrab

ERROR: PIO 'X0/Y53/PIOB' does not appear to be a DQS site (expecting an
'A' pin).
ERROR: Packing design failed.

Loc pio_loc = ctx->getBelLocation(pio_bel);
if (pio_loc.z != 0)
    log_error("PIO '%s' does not appear to be a DQS site (expecting an
'A' pin).\n",
     ctx->nameOfBel(pio_bel));

getBelLocation is defined by
Loc getBelLocation(BelId bel) const override
    {
        NPNR_ASSERT(bel != BelId());
        Loc loc;
        loc.x = bel.tile % chip_info->width + bel_data(bel).rel_x;
        loc.y = bel.tile / chip_info->width + bel_data(bel).rel_y;
        loc.z = bel_data(bel).z;
        return loc;
    }
    
bel_data comes from a model specific database I guess

Under https://github.com/YosysHQ/nextpnr/blob/master/docs/faq.md,
I read Bel: Basic Element, the functional blocks of an FPGA such as
logic cells, IO cells, blockrams, etc. Up to one cell may be placed at
each Bel.
so for a DQS site, loc.z must be zero, and PIOB is most likely not
zero, I guess that only PIOA is zero