[Libre-soc-dev] RS=RT+VL vs. RS=RT+MAXVL

[Jacob Lifshay]

Looking over the changes to the wiki:

> The significant part here is that the second half is stored
> starting not from RT+MAXVL at all: it is the *element* index
> that is offset by MAXVL, both halves actually starting from RT.
> If VL is 3, MAXVL is 5, RT is 1, and dest elwidth is 32 then the elements
> RT0 to RT2 are stored:
>
>          0..31     32..63
>     r0  unchanged unchanged
>     r1  RT0.lo    RT1.lo
>     r2  RT2.lo    unchanged
>     r3  unchanged RT0.hi
>     r4  RT1.hi    RT2.hi
>     r5  unchanged unchanged

No, that won't work well since there is no good way to run vector
instructions starting at something other than the beginning of a
register, making it hard to access the RS vector normally. (REMAP
technically would work, but I think we should fix our design so we're
not forced to need it here.)

setvl VL=5, MVL=5
sv.divrem2du/elwid=8 r80.v, r32.v, r48.v, r64.v
# now try to read RS:
sv.addi r32.v, r80.625.v, 1 # we can't address register 80.625 (80 +
5/8) since that's not an integer...

Instead, I think we should have RS round up to the next possible
vector starting location after RT+MAXVL (usually the next full
register, but it could be multiple registers if we later switch to 512
registers instead of 128).

Jacob