[Libre-soc-dev] proposal of change of register name convention in SVP64

[Lauri Kasanen]

On Mon, 27 Jun 2022 22:13:16 +0100
Luke Kenneth Casson Leighton via Libre-soc-dev
<libre-soc-dev at lists.libre-soc.org> wrote:

> due to the expression-parsing function in binutils taking the "0" as a
> number.
>
> if however the qualifier is in *front* of the register number then things
> get a lot easier.  ideas include:
>
>     sv.addi v.0,    # unfortunately this is already taken with VSX registers
>     sv.addi v:0,    # this is ok
>     sv.addi v!0,    # meh
>     sv.addi v at 0,  # also meh
>     sv.add V0, Vr1, Sr2      # uppercase is ok
>
> one important thing, is that the change should not be too radical so as to
> invalidate 2 years worth of videos.
>
> thoughts appreciated.

I prefer the "vr0" syntax, just prefix v, no dot, mentioned on IRC but
not in the mail. It's separate from the v0 VSX registers, and makes it
clear it's a vectorized scalar reg.

Easier to type without a symbol, and case-sensitiveness would be a big
no-no.

- Lauri