[Libre-soc-dev] SV Twin and Single Predication

[lkcl]

https://libre-soc.org/openpower/sv/svp64/appendix/#1p

such irony.  even after correctly implementing the predication algorithm in both the simulator and in TestIssuer, it is only now, 2 years after writing the spec, that i get a clear idea of how it actually works.

i had been under the mistaken impression that just because Single Predication has a single mask, that srcstep is forced to equal dststep at all times.

this is false!

sz and dz (skip-or-zero), can be *different*, even when the mask is the same because Single Predicate Mode is requested!  only when sz==dz (whether they are both zero or both 1) does srcstep equal dststep at all times.

i love that i am learning new things about SV, this is inevitable because it is so powerful. although i do feel a bit dumb at having missed this particular trick for so long.

l.