[Libre-soc-dev] Microwatt L1 cache snoop idea for future SMP

[lkcl]

hmmmm, i'm now wondering if it would be better to implement
cache_valids as a group of reset-priority SR-latches.  instead of:

                 -- Do invalidations from snooped stores to memory
                 for i in way_t loop
                     if snoop_valid = '1' and read_tag(i,
snoop_tag_set) = snoop_wrtag then
                         cache_valids(snoop_index)(i) <= '0';
                     end if;
                 end loop;

have this (pseudo-code):

    -- little trick of making the cache_valids a flat 1D vector
    cache_valids = vector(NUM_LINES * NUM_WAYS)
    cache_setme = vector(NUM_LINES * NUM_WAYS)
    cache_clrme = vector(NUM_LINES * NUM_WAYS)

    cache_clrme = 0
    for snooper in snoopers:
        for i in way_t loop
         if valid(snooper) etc:
           cache_clrme |= (1<<(snoop_index*NUM_WAYS)+i)

or

           cache_clrme[(snoop_index*NUM_WAYS)+i] <= 1

then:

    cache_valids |= cache_setme    -- set
    cache_valids &= ~cache_clrme -- reset takes priority

this *should* result in an OR-cascade of bitvectors that
are then neg-anded *once* into the cache_valids

l.