[Libre-soc-dev] [OpenPOWER-HDL-Cores] microwatt dcache potential bug (overlap r0 and r1)

[Luke Kenneth Casson Leighton]

ok the "hack" that i added, which is to stop r1.full from being
set to zero for mmu_reqs in RELOAD_WAIT_ACK seems to
work: that results in the incoming "std" request (the transfer
from r0 to r1.req) being delayed.

however in parallel with that (because it takes so damn long
to run) i've a *second* sim running with the (much better)
r1_next_full hack in place.  i will know whether this works
some time around 4am.

attached is a patch for dcache.py which shows the principle,
what i suspect is that either somehow the way that dcache.vhdl
interacts with loadstore.vhdl and mmu.vhdl this timing-related
issue is avoided, or that GHDL happens to have rules which
prioritise the multiple settings of r1.full=1/0 in a predictable
but totally unexpected (side-effect-style) way.

l.