[Libre-soc-dev] [OpenPOWER-HDL-Cores] microwatt dcache potential bug (overlap r0 and r1)

[Luke Kenneth Casson Leighton]

On Fri, Jan 14, 2022 at 4:27 AM Paul Mackerras <paulus at ozlabs.org> wrote:

> The value of r1.acks_pending is only relevant in STORE_WAIT_ACK state,
> and it is set correctly (to 1) on entry to that state from IDLE state,
> which is the only way we get to that state.

yehyeh.  i'm considering zeroing-out r1.acks_pending (and r1.req.op
etc.) at the point where r1.state is set to IDLE, just so get some
clarity but also to double-check it's not affecting anything.

> Fair enough; and it is possible that decoupling the update of
> r1.acks_pending from r1.state might result in simpler logic.
> However, I don't think we have identified any bug yet.  What exactly
> is the misbehaviour that you are seeing?

deep breath: i need to re-run a 3.5 hour verilator sim to get back
to that point, the one i started at 3:30am had the wrong pattern
to search for and didn't trigger vcd trace. sigh.  i'll have more
this afternoon.

l.