[Libre-soc-dev] peripheral and phy development for libre-soc and microwatt

[Luke Kenneth Casson Leighton]

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in bridging between both ASIC and FPGA worlds i have been analysing the
various Libre/Open PHYs and Peripheral Fabric Connects and they are limited
in a practical sense for larger cores (~45k LUT4s such as the 64-bit Libre-SOC
and Microwatt cores).

[note that Power ISA 32-bit cores - would be sufficiently low resources to
potentially not encounter this problem]

prior to Power ISA cores, most Libre/Open CPUs (OR1200, RV32*, m68000)
pushing even 5k LUT4s for the entire design are hard to find.  the upshot is
that they can run at quite high clockrates (one ULX3S developer has achieved
240 mhz on an ECP5 85k) because utilisation of the FPGAs is so low there is
plenty of headroom to get a successful route, and lower-resource FPGAs can
be utilised which have a greater chance of success in routing in the
first place.

this in turn means that a number of FPGA-targetted peripheral fabrics and
their associated PHYs are designed as *synchronous*, because it is easier
to do that way... oh and nobody before now needed anything else.

the fundamental assumption has been that the core rate *must* equal the
PHY rate.  litex for example requires that the DRAM PHY speed is *exactly*
equal to the main core speed.

* ~45k LUT4 cores however are so challenging to route that in the case of
 Libre-SOC on the 85k ULX3S it has only been possible to achieve 12.5 mhz
* [the version without the MMU and L1 I/D-Caches however achieved 55 mhz,
  because it only required around 17k LUT4s].
* Microwatt with symbiflow on the Arty-A7-100t was only possible to achieve
  around 35 mhz.

12.5 and 35 mhz are nowhere near fast enough to run the DRAM PHY when it is
hard-tied to the same speed by the peripheral fabric.

this has been solved for decades in the *ASIC* industry with asynchronous PHYs!

Rudi's USB2 PHY contains separated Wishbone and PHY clocks:
https://github.com/www-asics-ws/usb2_dev/blob/master/rtl/verilog/usbf_wb.v

Dinesh's SDRAM PHY contains separated Wishbone and PHY clocks:
https://github.com/freecores/sdr_ctrl/blob/master/rtl/wb2sdrc/wb2sdrc.v

Olof and Igor's 10/100 PHY contains separated Wishbone and PHY clocks:
https://github.com/freecores/ethmac/blob/master/rtl/verilog/ethmac.v

Richard Herveile's RGBTTL (VGA) PHY contains separated WB and PHY clocks:
https://github.com/RoaLogic/vga_lcd/blob/master/rtl/verilog/vga_pgen.v

Richard, Rudi and Dinesh's PHYs are all Silicon-proven, and all four PHYs
contain Asynchronous FIFOs that provide clean separation between the PHY
and the main core Memory bus (Wishbone).

therefore (getting to the point) what i intend to do is focus on
putting together
a peripheral fabric that utilises these Asynchronous PHYs, and have them
driven by multiple separate clocks from the FPGA's PLL.

this will make it easier to create ASICs from both Libre-SOC and Microwatt
in the future.

this will be in nmigen and if anyone would like to help you are most welcome
https://git.libre-soc.org/?p=ls2.git;a=blob;f=src/ls2.py;hb=HEAD

l.