[Libre-soc-dev] Coriolis 2 - Tutorials and check

[Luke Kenneth Casson Leighton]

On Sun, Aug 14, 2022 at 10:10 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> > [ERROR] CParsVst() VHDL Parser - File:<./cmpt_sram4k_0.vst> Line:418
> >         Port map assignment discrepency instance:0 vs. model:1
> >         Model: "vdd"
> >         Instance:
> >         Python stack trace:
> >         #0 in                scriptMain() at doDesign.py:36
>
> yes if you have not rebuilt alliance, it is no good running the same
> command with the same binary executables, you will of course get
> the same results.

Santosh i apologise, i have re-run these commands and can replicate
the issue.

unfortunately i have not been working on this in over 15 months so i have
absolutely no idea what the problem is and will have to stop everything that
i am doing in order to investigate it fully.

i will attempt to get the design compiled which does not need the PLL
or the 4k SRAMs, in FreePDK45.

l.