[Libre-soc-dev] RS=RT+VL vs. RS=RT+MAXVL

[Jacob Lifshay]

I was thinking about instructions like divrem2du:
I realized that it would be much better to have RS be RT + MAXVL rather
than RT + VL since MAXVL is almost always a compiler-known constant whereas
VL is often variable:
e.g. if RS=RT+VL then the compiler can't easily generate correct code:
li r3, 8 # for demo purposes, assume actually runtime variable
setvl r0, r3, MAXVL=16 # sets MAXVL = 16 and VL = min(MAXVL, r3)
sv.divrem2du r80.v, r32.v, r48.v, r64.v
# now try to read RS:
sv.addi r32.v, r88.v, 1

the sv.addi will only reads RS correctly if VL happens to be 8, otherwise,
if VL=16, it'll read part of RT and part of RS, even worse, if VL=4, then
it'll read completely past the end of RS.

Therefore I think RS should mean RT+MAXVL instead, since that gives a
compile-time predictable location for the RS output.

Jacob