[Libre-soc-dev] load/store quad and svp64

[Jacob Lifshay]

in
https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/svp64/appendix.mdwn;h=eb9fb4cb158a9379f122d1a9d2042948a133a136;hb=HEAD#l75

lq is stated to be excluded from svp64, imho it should be included since
128-bit atomic operations are very useful, even in vector code.

The 128-bit atomic operations (from the OpenPower ISA spec. v3.1 book 2
section 1.3):
lq
stq
lqarx
stqcx.

They can't be replaced by svp64 vectorized 64-bit load/stores unless svp64
is modified to additionally guarantee atomicity at the 128-bit size, which
I don't think is appropriate for 64-bit operations.

One example of where vectorized 128-bit atomics are quite useful is if
you're trying to vectorize lookups in a parallel hash table with 64-bit
key/value pairs, you'd want the 128-bit loads to be relaxed-atomic
operations since otherwise the key or value might be modified by some other
cpu and you'd get an old key and a new value or something like that rather
than the correct result of the old key and the old value, or the new key
and the new value.

OpenPower uses lq for 128-bit relaxed (monotonic in llvm ir) atomic loads,
as you can see here:
https://github.com/llvm/llvm-project/blob/7c5d5edec8abb7389b16f5a92107f2d8d4be94e1/llvm/test/CodeGen/PowerPC/atomics-i128-ldst.ll#L246

Jacob