[Libre-soc-dev] Libre-SoC 0.1

[lkcl]

On September 24, 2021 10:59:21 AM UTC, Veera <vklr at vkten.in> wrote:
>Hi,
>
>Libre-SOC 0.1 test chip is tapered out as I read in ml.
>I want to know what is it?

a fixed point Power ISA v3.0B compliant test ASIC.

>Is it the microwatt

no.

> designed by libre-soc team

yes.

> and term Libre-SOC 0.1?

it is called ls180.  it is on the wiki

>What features it has?

an absolute basic set of peripherals, accessible over wishbone, a JTAG interface, a PLL, four 4k SRAMs, and a dead simple core which is based around a Finite State Machine which completes one instruction approximately every 7-10 cycles.

l.