[Libre-soc-dev] Libre-SoC 0.1
luke.leighton at gmail.com
Fri Sep 24 16:16:08 BST 2021
On September 24, 2021 10:59:21 AM UTC, Veera <vklr at vkten.in> wrote:
>Libre-SOC 0.1 test chip is tapered out as I read in ml.
>I want to know what is it?
a fixed point Power ISA v3.0B compliant test ASIC.
>Is it the microwatt
> designed by libre-soc team
> and term Libre-SOC 0.1?
it is called ls180. it is on the wiki
>What features it has?
an absolute basic set of peripherals, accessible over wishbone, a JTAG interface, a PLL, four 4k SRAMs, and a dead simple core which is based around a Finite State Machine which completes one instruction approximately every 7-10 cycles.
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