[Libre-soc-dev] Vector Supercomputing ISA and 3D GPU resources
hendrik at topoi.pooq.com
Wed Sep 15 13:39:50 BST 2021
On Tue, Sep 14, 2021 at 06:18:34PM -0700, Jacob Lifshay wrote:
> On Tue, Sep 14, 2021, 18:12 Hendrik Boom <hendrik at topoi.pooq.com> wrote:
> > I remember hearing of one performance analysis that determined that some
> > of the most
> > used instrucions were conditional branches. So they werked very hard
> > optimising the
> > hardware for the next version of their machine for conditional branches.
> > Once they
> > built it there was NO improvement in speed. Investigating, they
> > discovered they had
> > optimized the wait loop.
> Oops...though realistically, optimizing the wait loop to go into lower
> power states and not spam the memory bus and resume faster does help,
> that's why x86 has the pause and monitor/mwait instructions and Arm has the
> yield instruction.
Optimizing the wait state makes sense. But they optimized the conditional
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