[Libre-soc-dev] Vector Supercomputing ISA and 3D GPU resources

lkcl luke.leighton at gmail.com
Wed Sep 15 06:41:42 BST 2021

On September 15, 2021 1:11:54 AM UTC, Hendrik Boom <hendrik at topoi.pooq.com> wrote:

>I remember hearing of one performance analysis that determined that
>some of the most 
>used instrucions were conditional branches.  So they werked very hard
>optimising the 
>hardware for the next version of their machine for conditional
>branches.   Once they 
>built it there was NO improvement in speed.  Investigating, they
>discovered they had 
>optimized the wait loop.

that's very funny.

it's what i am expecting that cavatools (Peter Hsu's work) will help with.

peter's simulator allows defining hardware latency characteristics.  how many cycles for L1 miss.  how to handle register write hazards.

there is then an inspection console highlighting what ia going on. when stalls occur etc.


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