[Libre-soc-dev] [RFC] SVP64 Condition Register ops
luke.leighton at gmail.com
Wed Sep 8 14:15:03 BST 2021
turns out that CR ops such as mfcr, crand, crxor, all need their own dedicated RM Modes. reason: you can't apply elwidth overrides, and arithmetic saturation makes no sense either.
i've therefore documented a slightly different arrangement for DD FFirst, and for Predicate-Result mode.
there is a remarkable similarity to the sv.bc instructions but the sv.bc instructions *do not* modify CRs, they only *read* CR bits.
Vectorised CR instructions *modify* CRs and the DDFF and PredRes modes then interact *with* those results [in similar ways to how sv.bc works]
comments and review appreciated
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