[Libre-soc-dev] snitch core

[Luke Kenneth Casson Leighton]

On Mon, Oct 25, 2021 at 10:43 AM Richard Wilbur
<richard.wilbur at gmail.com> wrote:
>
> On Sun, Oct 24, 2021 at 7:54 AM lkcl <luke.leighton at gmail.com> wrote:
> > it *might* be a Vertical-First, particularly if it is possible to zero-overhead-loop automatically around multiple instructions.
>
> Thanks for the link Jacob.  I read the article and there is a field in
> the loop control setup instruction that specifies how many
> instructions to loop over.  On page 6, "Figure 5. (a) Anatomy of the
> proposed FREP instruction."  lists an immediate field "number of ins.
> to repeat".

Mitch Alsup's MyISA 66000 does it by having a pair of instructions:
one to indicate the start of the loop, the other the end.

the start loop instruction also declares which register is the
loop-invariant counter, and, fascinatingly, declares which
registers are to be read-only-as-vectors and which are
writes.

this information goes directly into the Hazard Engine if an OoO
microarchitecture is deployed, making for greatly-simplified
designs, and it's pretty easy for a compiler to give the information.

l.