[Libre-soc-dev] snitch core

[lkcl]

On October 24, 2021 5:02:26 AM UTC, Jacob Lifshay <programmerjake at gmail.com> wrote:
>the unexpected part is where I found it: google news linked to a ieee(?
>could be misremembering) article about it.

interesting, and fortuitous.

>yup, snitch is a pulp-platform cpu.

ahh that sounds right. they are the ultra-low-power group.

ok so i had a look: figure 6 explains it, by doing incremental introductions of the two features.

feature 1: DSP style "zero overhead loop control" (ZOLC)

the version used is quite basic (and perfectly adequate), hilariously and ironically it is identical to the Simple-V technique we came up with over 3 years ago: repeat-context is established, repeat occurs.

it *might* be a Vertical-First, particularly if it is possible to zero-overhead-loop automatically around multiple instructions.

feature 2: CISC-like / CDC6600/PDP11/68000-like "auto-load-and-increment"

certain FP regs may be "tagged" to indicate, "if you *ACCESS* this register, actually what i want to happen is that you go off and read the register contents from memory (effectively) and by the way, auto-increment the load address to the next address as a side-effect"

this is pretty much the definition of CISC "load-and-increment" instructions, and is no surprise given that they are part of efficient / elegant designs from 50 years ago.

by making it a "tag" (exactly like how SVP64 REMAP works: that is also a hidden "tag" architecture) the underlying RISC architecture does not need changing.

the bit that is novel here is thus not the techniques, but how they demonstrated a hardware architecture that is power-efficient as a result.

good for them.  like it a lot.

l.