[Libre-soc-dev] Massive EU Grant (up to 26 million) deadline 21st Oct

[Jacob Lifshay]

On Sun, Oct 17, 2021, 02:27 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
>
>
> On Sun, Oct 17, 2021 at 4:11 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > On Sat, Oct 16, 2021, 07:26 lkcl <luke.leighton at gmail.com> wrote:
> >
> > > folks i noticed a few days ago a huge opportunity, an EU Grant that
> even
> > > says "Open Hardware/Software".
> > >
> >
> > ooh!
> >
> > >
> > >
> > >
> >
> https://ec.europa.eu/info/funding-tenders/opportunities/portal/screen/opportunities/topic-details/horizon-cl4-2021-digital-emerging-01-01
> >
> >
> > Noticed it includes "Proposals should include research on advanced
> > hardware-based security at silicon-level",
>
>
> the one that i am putting in which definitely qualifies is to use this
> technique:
> https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1977-05.pdf
>
> wires distributed strategically throughout the processor with analog
> ring circuits (a PLL in effect) will be affected by local EMF.  thus by
> running
> any given program, the frequency will change (HP's Signature Analysis
> was a bit more sophisticated but you get the idea).
>
> it then becomes possible to create an audit trail showing the results of
> running a program and if the silicon was ever tampered with (some rogue
> unauthorised transistors) they will show up *even if not active* because
> they will change the layout characteristics.
>

neat! hopefully that pll isn't the cpu clock, otherwise anyone who can see
the packets your sending over the network (or introspect cpu timing some
other way) is essentially given a built-in awesome emi detector, making it
easy to detect whatever secret data (AES keys anyone?) you're processing.

>
> sounds like the idea I came up
> > with for meltdown/spectre-proof (for timing/cache/etc. side-channels --
> > *not* for power side-channels) speculative execution:
> > https://bugs.libre-soc.org/show_bug.cgi?id=209
> >
>
> it's close enough so yes.
>
> bear in mind we'll still be under time pressure and have chosen
> the Scoreboard system due to its power consumption saving, so
> the "Shadow/Cancellation" system will need to be part of that.
>

the meltdown/spectre-proof idea is applicable to that microarchitecture
too, it applies to nearly any out-of-order microarchitecture.

I do want to have a traditional register-renaming microarchitecture as one
of the demo cpu's supported microarchitectures -- since that's what's used
by a lot of mainstream processors, so others can see that the idea isn't
specific to our 6600-based microarchitecture -- the idea is that others can
use the spectre-proof idea in their own cpu designs too, thereby making the
whole cpu industry more secure.

The register-renaming microarchitecture shouldn't be too hard to implement
(I've already thought through a lot of it), I'd guess a few weeks for the
register-renaming/scheduler -- the rest should be able to be shared with
the 6600-based design.

a demo of a decent portion of the register-renaming/scheduling algorithm:
https://ftp.libre-soc.org/power-cpu-sim/

Jacob