[Libre-soc-dev] LibreSOC Implementation on arty7 fpga dev boards.

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Tue, Oct 5, 2021 at 6:05 PM varun mohan <varunmadhavam at gmail.com> wrote:
>
> Hi Luke,
>
> > this is *not* a difficult task if you are an experienced python
> programmer.
> > it should be well under 45 minutes of work and *only* result in around
> > 40-50 lines of code, absolute maximum.
>
> I have very basic knowledge of python but I tried. I have created a new
> fpga.py file with the suggested modifications. for the time being, kept here
> <https://gist.github.com/varunmadhavam/10e8fd9f94b16fe203a8e07301cbbdcc>

hey that looks brilliant, it's exactly as i would expect it to look.  you got
the variant="a7-100", toolchain="symbiflow", all the other args were
copied from the other two BaseSoCs, i'd expect that to work

> But while trying to generate the bitstream, I am hitting an error. Looks
> like it's while trying to compile some firmware for the SOC. Entire error
> log is kept here
> <https://gist.github.com/varunmadhavam/bd9ec6a81d2e1caa9a66323a909c6c2e>
> Can you please have a look and may be help to resolve the issue.

*sigh* that is very familiar, and down to using too modern (too recent) versions
of litex.

under enormous time pressure i got things running, and had to "freeze" (use)
a version of litex that was up-to-date about... 15 months ago.

Las (the user on #libre-soc IRC libera chat) managed to get through this
by *back-dating* the version of litex *and all its dependencies) manually
checking out the required git commit versions around that time, and of course
i can't now remember where that was.  we _did_ document it...

not here...https://libre-soc.org/irclog/%23libre-soc.2021-09-26.log.html

here you have to make sure you use the right version of nmigen and yosys:
https://libre-soc.org/irclog/%23libre-soc.2021-09-25.log.html

got it!  here's the list.  you'll have to "git checkout xxxxxxxx" manually
in each subdirectory then apply the patch shown:

https://bugs.libre-soc.org/show_bug.cgi?id=700

i've added that bugreport to this page:
https://libre-soc.org/HDL_workflow/litex_ls180/

if you could extract that list from the bugreport and put the names
of the litex sub-repos into the page that would be real handy.

apologies we haven't yet had time to do a script for this.  if you'd
like to help write one that would be great, it would help everyone.
it can go in the dev-env-setup scripts, if you are happy with the Charter
and send me an ssh public key, you can add it yourself.

l.