[Libre-soc-dev] Greetings -> spice netlist

[lkcl]

On Sat, Nov 20, 2021 at 1:30 AM D. Mitch Bailey
<d.bailey at shuharisystem.com> wrote:

> > Thanks, that should be enough to keep me busy for a couple days.
> I was wrong about that. Couldn't find anything that even remotely
> resembled a transistor level spice netlist.

like i said: you'll need to auto-generate it by running a python script
or potentially having to examine the coriolis2 source code and write
one (hunting through the git commit logs will help find exactly what
was added and how).

> The vbe files appear to be behavioral models.

yes.

> Maybe that's because the transistor W/L are tied to a closed PDK.

not at all. nsxlib was developed entirely Libre and is silicon-proven
in 350nm and 180nm, there is a collaboration with a Japanese
University there, i cannot recall the exact details.

the alliance file (ap) contains the transistors.  each VBE
file has a corresponding .AP file.  .AP files are similar to GDS-II
except they allow only rectangles, not polygons.

if you install coriolis2 you can open the cells and see them.

$ cd soclayout/experiments9
$ make cgt
$ cp ~/alliance-check-toolkit/cells/niolib/gpio* .
File | Open Cell
type "gpio" return

(in this case, gpio.ap is not particularly sophisticated, and
may even be a "dummy" - i don't know - but ao22_x2.ap clearly is
not fake/dummy)

you can install coriolis2 with this script:
https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=coriolis2-chroot;hb=HEAD

instructions are here:
https://libre-soc.org/HDL_workflow/coriolis2/

l.
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