[Libre-soc-dev] bitmanip planning

[lkcl]

On November 4, 2021 9:55:44 PM UTC, Jacob Lifshay <programmerjake at gmail.com> wrote:

>Lkcl, where is the reference verilog?

much of the complex ones that csme from RISCV xbitmanip went into picorv32 or into claire wolfe's repos.

gaah this was a pain to find:


https://github.com/cliffordwolf/xbitmanip/tree/71a19aad81369fbcf71b83e78564e0c8ee1b1b80/verilog


can i recommend starting with ridiculously small and obvious ones like bitset / bitclear? [watch out that some bitmanip ops are already in Power ISA. i think i caught most of them]

or with standalone modules like shuffle or grev (following how things were done with bpermd and popcnt)?

this will give time to work out opcodes and CSV files which both HDL and ISACaller depend on.

a fun one is the ternary one.

still TODO, work out what actually goes in, and, also, sigh, discuss Galois Field.  that is *FOUR* input registers (!) FIVE if adding a GF-MAC! (NTT needs GF-MAC) two of those really need to be SPRs, the modulo and the power.

l.