[Libre-soc-dev] NGI POINTER gigabit ethernet router ASIC roadmap

[lkcl]

On November 1, 2021 1:27:30 PM UTC, Andrey Miroshnikov <andrey at technepisteme.xyz> wrote:

>Started looking at the wiki page
>https://libre-soc.org/shakti/m_class/pinmux/
>
>The page points to bug #8, and pinouts wiki page.
>
>The page mentions CMOS push-push on several occasions. The usual term 
>related to IO is *push-pull*

ah do correct that.  it is intended to indicate, "not the other type which is open drain and / or has pullup / pulldown resistors"
>As for the task, should I be looking at the following directory:
>/soclayout/pinmux/

pinmux repo, git.libre-soc.org

>and then testing out the examples, see what functionality is missing?

all of it.

there is a bluespec fabric generator (working fine, try the iclass example i think, but don't ask me too many questions about code i wrote in a hurry for IIT Madras back in 2018)

there is *no* nmigen fabric generator.  i started a myhdl one but that was before using nmigen.

>For LS180, was the pinmux generated manually?

of course not, that would be quite insane to have four duplicated copies of pin maps, hand written documentation and hand written SVG files.

we are software engineers not 1980s "what's git and what's python, and what are unit tests for" hardware engineers!

the pinmux program is actually really sophisticated densely-packed data structure manipulation, encoding relationships between "requested pins" and "actual pins".

in ls180 i did not however actually add any "muxing", every pin is single-function.

i would very much *like* to have GPIO muxing this tine, not least because the EUR is there to do it, snd because the mapping of available pins in a package down to available pads might not be enough

(each RGMII interface is 20 pins, there are 5)

however we do have to be extremely careful because there are implications here for the design.

l.