[Libre-soc-dev] PLL integration

[Luke Kenneth Casson Leighton]

On Wed, May 26, 2021 at 2:48 PM Marie-Minerve Louerat <
Marie-Minerve.Louerat at lip6.fr> wrote:

>
> I recall our previous request to be able to perform the verification:
>

thank you for the reminder of the checklist, alway appreciated.


>
> > Therefore, on :
> >
> > - 4 May, we request that the design is stabilized, thus:
> >
> >   * select Verilog OR RTLIL as the input behavioral description
> >     language for YOSYS
>

done.  changed to verilog 6 weeks ago due to instability in yosys.

>   * validate the description after YOSIS synthesis with simulation
> >     patterns (+ RAM, + JTAG)
>

done, needs re-running

>   * freeze the behavioral description (in the selected format)
>

impractical at the moment whilst we are resolving things like PLL signal
names.

>   * freeze Yosys version
>

done 8 weeks ago

>   * commit the above selection in the "soclayout" git of LibreSoC with
> >     a dedicated tag,
>

can be done only once frozen which requires basic naming issues to be
resolved, and it involves about 8 or 9 repositories so i am reluctant to
commit to it until we know for certain that stability has been achieved.

l.