[Libre-soc-dev] [OpenPOWER-HDL-Cores] load/store conditional

[Benjamin Herrenschmidt]

On Tue, 2021-05-25 at 11:10 -0700, Jacob Lifshay wrote:
> 
> I think the issue is not how many instructions can be put between LR
> and SC, since both OpenPower and RISC-V have no limit, but instead:
> how many and which kind of instructions can be put in between a LR
> and SC while retaining an architectural forward-progress guarantee.
> Just snooping and deleting the reservation is not sufficient if you
> want a forward-progress guarantee, since it is totally possible for
> the following loop to live-lock:
> loop:
> lwarx r5,0,r3
> stwcx. r4,0,r3
> bne loop
> 
> The following assumes lwarx is implemented by obtaining the cache
> block in the Exclusive or Modified states in the MESI cache coherency
> protocol.
> Assume two cpu threads T1 and T2 are both executing the loop:


 .../...

Ah yes, this is an issue on POWER as well, there's I think quite a bit
of logic for livelock busting. Among other things, you can use an lfsr
to introduce randomness, and you can have some kind of livelock
"detection".

>From vague memories, I think it is recommended that software doesn't
leave reservations dangling forever, but I'm not 100% sure, so
implementations need to be resistant, especially since those are
userspace resources.

Cheers,
Ben.