[Libre-soc-dev] PLL integration

[whygee at f-cpu.org]

On 2021-05-25 19:09, Luke Kenneth Casson Leighton wrote:
> success, P&R completes on NDA-free experiments9 nsxlib with
> "fake" PLL and 4x 4k SRAM blocks.  no missing / loose nets.
> 
> over to you, Jean-Paul, anything missing / blockers let me know.
> 
> l.

Congratulations !

As the Germans say : "Puh das war Harter Stoff"