[Libre-soc-dev] PLL integration

[Jean-Paul Chaput]

Hello Dimitri, Luke & Al,

There is no urgency for you to rename that signal. Just be aware that in
the complete chip, it is renamed into "out_v".

I should have finally solved the DRC errors, the problem was mine,
the GDS parser was not handling correctly GDS records PATH of type 4,
that is with variable extension length. But the "vendor" driver seems
to like them a lot (to make just straight wires, which is overkill).

So the previous errors about misaligned rectangles are corrected
and the METAL1 DRC errors goes away. I did perform a DRC on the
PLL GDS as driven *back* by Coriolis. Seems OK. Along with a visual
inspection with KLayout no obvious differences.

*But*, now I get LUP.1g and LUP.2g errors in the PLL, when inserted
into the chip. From what I understand, some kind of guard ring is
missing. The complete GDS file is my account ~jpc/chip_r.gds with
the top cell named "chip_r". Could you take a look and see what's
wrong. It is not impossible that I still botch your PLL GDS, so
don't hesitate to check that the layout is really what you did
draw.

For Luke, can you tell me when the updated netlist with the PLL
connected is available ?

Best,



> Tue, 2021-05-25 at 09:07 +0200, dimitri.galayko at lip6.fr wrote:
> Dear all, 
> 
> Sorry, I have overlooked this point. 
> 
> Do you want me to rename the « out » signal in the provided PLL design ? It is easy to
> do.  
> 
> Best regards 
> 
> Dimitri 
> 
> > Le 22 mai 2021 à 11:21, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> a écrit :
> > 
> > 
> > Hello Luke,
> > 
> > I am now in the final stage of the PLL integration and I am wondering
> > it it is correctly connected in the verilog I got. From what I can
> > guess "ref" goes straight to "out" and "a1" is hard-wired to "0".
> > 
> > I am on commit 3168ed1 of soclayout (after 5faa53a).
> > 
> > Best,
> > -- 
> > 
> >      .-.     J e a n - P a u l   C h a p u t  /  Administrateur Systeme
> >      /v\     Jean-Paul.Chaput at lip6.fr
> >    /(___)\   work: (33) 01.44.27.53.99              
> >     ^^ ^^    cell:      06.66.25.35.55   home: 09.65.29.83.38
> > 
> >    U P M C   Universite Pierre & Marie Curie
> >    L I P 6   Laboratoire d'Informatique de Paris VI
> >    S o C     System On Chip
> 
> 
-- 

      .-.     J e a n - P a u l   C h a p u t  /  Administrateur Systeme
      /v\     Jean-Paul.Chaput at lip6.fr
    /(___)\   work: (33) 01.44.27.53.99              
     ^^ ^^    cell:      06.66.25.35.55   home: 09.65.29.83.38

    U P M C   Universite Pierre & Marie Curie
    L I P 6   Laboratoire d'Informatique de Paris VI
    S o C     System On Chip