[Libre-soc-dev] PLL integration

[dimitri.galayko at lip6.fr]

Dear all, 

Sorry, I have overlooked this point. 

Do you want me to rename the « out » signal in the provided PLL design ? It is easy to do.  

Best regards 

Dimitri 

> Le 22 mai 2021 à 11:21, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> a écrit :
> 
> 
> Hello Luke,
> 
> I am now in the final stage of the PLL integration and I am wondering
> it it is correctly connected in the verilog I got. From what I can
> guess "ref" goes straight to "out" and "a1" is hard-wired to "0".
> 
> I am on commit 3168ed1 of soclayout (after 5faa53a).
> 
> Best,
> -- 
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