[Libre-soc-dev] PLL integration

[Jean-Paul Chaput]

On Mon, 2021-05-24 at 21:46 +0100, Luke Kenneth Casson Leighton wrote:
> On Monday, May 24, 2021, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> wrote:
> 
> > 
> > Yes... In my wrapper I did rename it automatically into "out_v".
> > 
> > I add "_v" to any VHDL keyword used as identifier.
> > I would prefer to keep, as much as possible, to stick to the original
> > names because they match the ones of the GDSII supplied by Dimitri.
> 
> 
> except, the name is "out" in the GDSII file.

  Not a problem. I can rename it as I like. The GDSII file is never
  used "directly". Is parsed inside Coriolis then used.

> therefore the wrapper creates the wrong name (v_out)

  The wrapper I'm talking about is in the TSMC NDA covered that
  you don't have. So, from where "v_out" do come from ?
  There is an information I may be missing here.

> therefore it is impossible to join up the nets because there is no way to
> connect out_v to out.


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