[Libre-soc-dev] PLL integration

[Luke Kenneth Casson Leighton]

arrgh, the word "out" - a name of a signal in the PLL - is a VHDL keyword,
isn't it?

can we rename the signals in the GDS-II file to "pll_out", "pll_a0",
"pll_a1" and so on?

l.