[Libre-soc-dev] PLL integration

[Jean-Paul Chaput]

On Sat, 2021-05-22 at 12:33 +0100, Luke Kenneth Casson Leighton wrote:
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> 
> > > a0 and a1 are the mux selection pins.  if they are hardwired to zero then
> > > there is no way to control the internal operation and selection of
> > > frequencies by the divider.
> > 
> >   OK. But now that I'm doing the final chip, I would need the true
> >   connexions. I may correct myself the "libresoc.v" netlist.
> > 
> 
> that would place you in the position of being an irrevocable and permanent
> maintainer of an extremely large and complex auto-generated file, i do not
> recommend it at all.

  Far from me this idea. I This was just to check it quick while
  you reviewed it.


> with the auto-generated output containing line numbers from the python
> source - which change - and with litex failing to properly keep stable
> names, any updating and merging would be an extreme nuisance.
> 
> 
> >   * I/O pads for a0 & a1.
> >   * "clk" of "ti" connected to "out" of PLL.
> >   * "ref" of PLL connected to "clk" of "test_issuer".
> > 
> 
> please let me deal with it.  i have created a new "Instance" submodule, and
> am restoring the original names so that Dimitry's PLL is wrapped inside
> another module.
> 
> this ensures that the names of the signals which (had) been stable and
> chosen for one year remain stable and do not change.

  OK. Will start to check it tomorrow afternoon.

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