[Libre-soc-dev] PLL integration

[Luke Kenneth Casson Leighton]

On Sat, May 22, 2021 at 11:12 AM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:


> a0 and a1 are the mux selection pins.  if they are hardwired to zero then
> there is no way to control the internal operation and selection of
> frequencies by the divider.
>
>
ok try this
https://git.libre-soc.org/?p=soclayout.git;a=commitdiff;h=75557957becdbb450f391212c8256003a271e801