[Libre-soc-dev] PLL integration

[Jean-Paul Chaput]

Hello Luke,

I am now in the final stage of the PLL integration and I am wondering
it it is correctly connected in the verilog I got. From what I can
guess "ref" goes straight to "out" and "a1" is hard-wired to "0".

I am on commit 3168ed1 of soclayout (after 5faa53a).

Best,
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