[Libre-soc-dev] MVL unclear

[Luke Kenneth Casson Leighton]

---
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On Fri, May 21, 2021 at 12:56 PM Lauri Kasanen <cand at gmx.com> wrote:


> >   8:  setvl  t0, a0           # vl = t0 = min(mvl, n)
>
> This will fail to compile because the compiler knows there are only 128
> registers.
>

nono: it's a *runtime* quantity.  VL is a *runtime* dynamically-settable
quantity.

thus it is impossible *at runtime* for the compiler to know what the
program will end up having in the loop (DAXPY of 10,000 values,
DAXPY of 50 values).


> Sorry, still not understanding why is it essential. To my reading, it's
> a completely useless duplication of VL, because you end up calling
> setvl with VL=MVL every time.
>

absolutely not.  no.  this is a fundamental misunderstanding of Vector ISAs.

this is very easy to refute: if you go through that example, then on the
very last loop, with MVL=64 and the entry parameter n=10,000, each
loop will perform 64 Vector operations (VL==MVL) *UNTIL THE LAST LOOP*.

10,000 - 64 - 64 - 64 .... etc. etc. until a0 gets down to these values

144
80
and finally...
16.

here, on this *last loop*, clearly and patently VL *IS NOT* equal to MVL.

* MVL == 64
* VL == 16.

see slide 12, here:
https://inst.eecs.berkeley.edu/~cs152/sp18/lectures/L16-RISCV-Vectors.pdf

this is really fundamental and critically important to understand, that it
is
the last iteration through the loop that is the whole reason why Cray-Style
Vector ISAs are efficient.

with it being *even possible* for VL to be less than MVL on the last
loop, *this is the whole entire reason why SIMD stupidity is not needed*.

with the last loop entry being possible for 0 <= VL <= MVL, Cray-style
Vectors cover *ALL* repeat *ALL* the ridiculous cleanup cases you see
in every single SIMD assembly listing.

l.