[Libre-soc-dev] MVL unclear

[Luke Kenneth Casson Leighton]

On Fri, May 21, 2021 at 12:35 PM Lauri Kasanen <cand at gmx.com> wrote:

> Hi,
>
> I've read the entire openpower/sv section, and it's still unclear to
> me what exactly is the point of MVL. Nowhere is it stated clearly what
> implications are setting it low and setting it high. Nor why is it
> limited to 64 when there are 96 extra registers.
>

it's a static compile-time declaration of the absolute maximum quantity
of registers that may be permitted to be used *at runtime*.

let us imagine that MVL does not exist as a concept, and attempt to
implement DAXPY.  take the example here:
https://www.sigarch.org/simd-instructions-considered-harmful/

let us imagine that the loop amount has been set to 10,000 on
calling the function.

  8:  setvl  t0, a0           # vl = t0 = min(mvl, n)

at the very first call of setvl, because no "limit" (*Maximum* Vector
Length, aka MVL) has been set, vl is set to 10,000, t0 is set to
10,000.

given that there are not 10,000 FPRs, only 128, this is a completely
useless design of the instruction "setvl".

it now becomes necessary to have *two* instructions where one
would do (actually, even more if there is no hardware integer "min"):

     cmpi a0, 8 # we have no MVL, must do the equivalent of MVL manually
     blt limit_ok
     addi a0, r0, 8
limit_ok:
     setvl t0, a0 # now and only now is this "safe" (under limit of MVL)

it's basically absolutely essentlal, and has been a fundamental part
of Cray-style Vectors for decades.

the difference with SVP64 is that MVL can be variable, where in
"traditional" Vector ISAs it is hard-coded at the actual fundamental
micro-architectural level, representing the actual number of back-end
SIMD "lanes" in the actual hardware.

l.