[Libre-soc-dev] microwatt / libresoc dcache

[Benjamin Herrenschmidt]

On Wed, 2021-05-12 at 06:06 +0100, Luke Kenneth Casson Leighton wrote:
> On Tue, May 11, 2021 at 10:55 PM Benjamin Herrenschmidt
> <benh at kernel.crashing.org> wrote:
> 
> > I'll let Paul comment on the TLB, that's his work, but as for delays,
> > the biggest issues we have on FPGAs aren't so much logic delays but
> > wire delays. "wires" in FPGAs are slow and BRAMs impose placement
> > constraints, especially when you have large (N*64-bit) busses going
> > in/out. Keep in mind that microwatt targets entry level FPGAs such as
> > the little Artix in the Arty board with -1 speed grades.
> 
> ahh this was where the 40mhz limit came from, is that right?

Possibly. On Artix we used to run it at 100Mhz.

> all FPGAs and FPGA toolchains not being equal, you may be fascinated
> to know that we ran into exactly the same resource utilisation in yosys
> that's been widely reported for microwatt builds on ECP5 + nextpnr5 + yosys,
> when we direct-ported dcache.vhdl into nmigen for use in Libre-SOC.
> 
> (it was so bad that it caused yosys to eat 34 GB of resident RAM and
> had the loadavg well over 40 on my 8-core i9 laptop with 64 GB of RAM!)
> 
> on a practical note, then: i notice that microwatt has 4 "ways" in the TLB.
> perhaps halving that to 2 for resource-constrained FPGAs (and providing
> it as a compile-time option) would help?

It's a compile time option isn't it ?

> (i did notice - cc'ing Anton - that there was a commit message about
> doing exactly this, for sky130A).
> 
> Minerva (an open source RV32 core) has only a 2-way set
> on its caches.
> https://github.com/lambdaconcept/minerva/blob/0b5f6b2466367f262f9a16a83f9c86fc7f008edf/minerva/cache.py#L19

Cheers,
Ben.