[Libre-soc-dev] [OpenPOWER-HDL-Cores] microwatt / libresoc dcache

[Benjamin Herrenschmidt]

On Fri, 2021-05-07 at 04:57 +0100, Luke Kenneth Casson Leighton wrote:
> 
> i think what i am saying is that cache_ram.vhdl having the ADD_BUF
> delay inside *cache_ram.vhfl itself* is completely unclear.

It has to be inside cache_ram.vhdl for the synthesizer to properly
infer it as the BRAM built-in output buffer rather than trying to
create some arbitrary register elsewhere in the FPGA.

It's a Xilinx'ism

Cheers,
Ben.