[Libre-soc-dev] daily kan-ban update 04may2021

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Tue, May 4, 2021 at 7:18 PM Tobias Platen
<libre-soc at platen-software.de> wrote:

> Yes I have read all emails I have got. First I had a look to mmu/fsm.py
> line 351 to 366. spr1_o.data is set to spr and a_i is ignored. They
> both need to be passed to the SPR regfile. spr1_i.data is still unused.

should be exactly the same as spr main_stage.py
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/spr/main_stage.py;hb=HEAD

except, of course, also placing a *copy* of the data into the local
dsisr, dar, etc. etc.

you'll need to think through all read/write scenarios, to make sure
the cached copy is up-to-date with the value that ends up in the SPR
regfile.

for example:

* LD/ST exception occurs, DAR/DSISR is overwritten *in the cached
copies only* (LoadStore1)
* MFSPR instruction is issued, value is read *from the SPR regfile*
not the cached copy in LoadStore1.

this would be a severe problem.

l.