[Libre-soc-dev] dcache and mmu linked up

[Luke Kenneth Casson Leighton]

On Monday, May 3, 2021, Tobias Platen <libre-soc at platen-software.de> wrote:

>
> I have been thinking about error handling long time ago. Setting the
> DSISR and DAR registers needs to be done, I had looked into the
> microwatt source code to find out how it is done there.


https://github.com/antonblanchard/microwatt/blob/master/loadstore1.vhdl#L735

we do not exactly have an equivalent of loadstore1.vhdl, so the SPR get/set
for DSISR, DAR, PGTBL and PIDR *all* have to be in mmu/fsm.py

mmu/fsm.py must be responsible for setting and getting ldst.dsisr and
ldst.dar via MTSPR / MFSPR

then, LoadStore1, on detecting an error, can set the required bits.

however this is where it gets slightly complicated.

if an error occurs it must be notified as a "result" of the pipeline
output, back to the TestIssuer.

however as of right now *there is no such mechanism*, one will have to be
added.  what *does* exist is, in PowerDecoder2, that if an exception is
*required*, one can be raised.

it does mean though that one cycle the Issuer FSM is executing a LD/ST, the
next cycle it's running an exception jump.

this will have to be fed from LoadStore1, through PortInterface, to
LDSTCompUnit, picked up by core.py, passed back to TestIssuer *and finally*
TestIssuer can set the "exception" flag in PowerDecoder2.

Tobias if you can make sure that mmu/fsm.py can get/set DSISR and DAR, this
will be a good first step.  they should be stored/read in LoadStore1 but
PLEASE REMEMBER, you STILL have to also put DSISR DAR PRTBL and PIDR out
through the spr1_o to get it into the SPR regfile.  the values stored in
mmu/fsm.py are *cached* values.

l.



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